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MC34023, MC33023 High Speed Single-Ended PWM Controller
The MC34023 series are high speed, fixed frequency, single-ended pulse width modulator controllers optimized for high frequency operation. They are specifically designed for Off-Line and DC-to-DC converter applications offering the designer a cost-effective solution with minimal external components. These integrated circuits feature an oscillator, a temperature compensated reference, a wide bandwidth error amplifier, a high speed current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle-by-cycle current limiting, and a latch for single pulse metering. The flexibility of this series allows it to be easily configured for either current mode or voltage mode control.
Features
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16 1
PDIP-16 P SUFFIX CASE 648
16 1
SOIC-16W DW SUFFIX CASE 751G
* * * * * * * * * * * * * *
50 ns Propagation Delay to Output High Current Totem Pole Output Wide Bandwidth Error Amplifier Fully-Latched Logic with Double Pulse Suppression Latching PWM for Cycle-By-Cycle Current Limiting Soft-Start Control with Latched Overcurrent Reset www..com Input Undervoltage Lockout with Hysteresis Low Startup Current (500 mA Typ) Internally Trimmed Reference with Undervoltage Lockout 90% Maximum Duty Cycle (Externally Adjustable) Precision Trimmed Oscillator Voltage or Current Mode Operation to 1.0 MHz Functionally Similar to the UC3823 Pb-Free Packages are Available*
16 4 5 6 Oscillator 13 VC Output 12 Power Ground 5.1V Reference 15 VCC
MARKING DIAGRAMS
16 16 MC34023P AWLYYWWG 1 1 A WL YY WW G = = = = = Assembly Location Wafer Lot Year Work Week Pb-Free Package MC33023DW AWLYYWWG
PIN CONNECTIONS
Error Amp Inverting Input 1 Error Amp 2 Noninverting Input Error Amp Output 3 Clock 4 RT 5 CT 6 Ramp 7 Soft-Start 8 (Top View) 16 Vref 15 VCC 14 Output 13 VC 12 Power Ground 11 Current Limit Reference 10 Ground 9 Current Limit/ Shutdown
Vref Clock RT CT
UVLO
7 Ramp Error Amp 3 Output Noninverting Input 2 Inverting Input 1 8 Soft-Start
14 Error Amp Latching PWM
11 Current 9 Limit Ref Current Limit/ Shutdown
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
Soft-Start
10 Ground This device contains 176 active transistors.
Figure 1. Simplified Application
(c) Semiconductor Components Industries, LLC, 2005
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 1 Publication Order Number: MC34023/D
October, 2005 - Rev. 6
MC34023, MC33023
ORDERING INFORMATION
Device MC33023DW MC33023DWG MC33023DWR2 MC33023DWR2G MC34023P MC34023PG Package SOIC-16W SOIC-16W (Pb-Free) SOIC-16W SOIC-16W (Pb-Free) PDIP-16 PDIP-16 (Pb-Free) Shipping 47 Units / Rail 47 Units / Rail 1000 Units / Reel 1000 Units / Reel 25 Units / Rail 25 Units / Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
MAXIMUM RATINGS
Rating Power Supply Voltage Output Driver Supply Voltage Output Current, Source or Sink (Note 1) DC Pulsed (0.5 ms) Current Sense, Soft-Start, Ramp, and Error Amp Inputs Error Amp Output and Soft-Start Sink Current Clock and RT Output Current Power Dissipation and Thermal Characteristics SO-16L Package (Case 751G) Maximum Power Dissipation @ TA = + 25C Thermal Resistance, Junction-to-Air DIP Package (Case 648) Maximum Power Dissipation @ TA = + 25C Thermal Resistance, Junction-to-Air Operating Junction Temperature Operating Ambient Temperature (Note 2) MC34023 MC33023 Storage Temperature Range Symbol VCC VC IO 0.5 2.0 Vin IO ICO -0.3 to +7.0 10 5.0 V mA mA Value 30 20 Unit V V A
PD RqJA PD RqJA TJ TA Tstg
862 145 1.25 100 +150 0 to +70 -40 to +105 -55 to +150
mW C/W W C/W C C
C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
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ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kW, CT = 1.0 nF, for typical values TA = + 25C, for min/max values TA
is the operating ambient temperature range that applies [Note 2], unless otherwise noted.) Characteristic REFERENCE SECTION Reference Output Voltage (IO = 1.0 mA, TJ = + 25C) Line Regulation (VCC = 10 V to 30 V) Load Regulation (IO = 1.0 mA to 10 mA) Temperature Stability Total Output Variation over Line, Load, and Temperature Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = + 25C) Long Term Stability (TA = +125C for 1000 Hours) Output Short Circuit Current OSCILLATOR SECTION Frequency TJ = + 25C Line (VCC = 10 V to 30 V) and Temperature (TA = Tlow to Thigh) Frequency Change with Voltage (VCC = 10 V to 30 V) Frequency Change with Temperature (TA = Tlow to Thigh) Sawtooth Peak Voltage Sawtooth Valley Voltage Clock Output Voltage High State Low State ERROR AMPLIFIER SECTION Input Offset Voltage Input Bias Current Input Offset Current Open-Loop Voltage Gain (VO = 1.0 V to 4.0 V) Gain Bandwidth Product (TJ = + 25C) Common Mode Rejection Ratio (VCM = 1.5 V to 5.5 V) Power Supply Rejection Ratio (VCC = 10 V to 30 V) Output Current, Source (VO = 4.0 V) Output Current, Sink (VO = 1.0 V) Output Voltage Swing, High State (IO = - 0.5 mA) Output Voltage Swing, Low State (IO = 1 mA) Slew Rate PWM COMPARATOR SECTION Ramp Input Bias Current Duty Cycle, Maximum Duty Cycle, Minimum Zero Duty Cycle Threshold Voltage Pin 3(4) (Pin 7(9) = 0 V) Propagation Delay (Ramp Input to Output, TJ = + 25C) SOFT-START SECTION Charge Current (VSoft-Start = 0.5 V) Discharge Current (VSoft-Start = 1.5 V) Ichg Idischg 3.0 1.0 9.0 4.0 20 - mA mA IIB DC(max) DC(min) Vth tPLH(in/out) - 80 - 1.1 - -0.5 90 - 1.25 60 -5.0 - 0 1.4 100 mA % V ns VIO IIB IIO AVOL GBW CMRR PSRR ISource ISink VOH VOL SR - - - 60 4.0 75 85 0.5 1.0 4.5 0 6.0 - 0.6 0.1 95 8.3 95 110 3.0 3.6 4.75 0.4 12 15 3.0 1.0 - - - - - - 5.0 1.0 - mV mA mA dB MHz dB dB mA V V/ms kHz fosc Dfosc/DV Dfosc/DT VOSC(P) VOSC(V) VOH VOL 380 370 - - 2.6 0.7 3.9 - 400 400 0.2 2.0 2.8 1.0 4.5 2.3 420 430 1.0 - 3.0 1.25 - 2.9 % % V V V Vref Regline Regload TS Vref Vn S ISC 5.05 - - - 4.95 - - - 30 5.1 2.0 2.0 0.2 - 50 5.0 - 65 5.15 15 15 - 5.25 - - -100 V mV mV mV/C V mV mV mA Symbol Min Typ Max Unit
1. Maximum package power dissipation limits must be observed. 2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0C for MC34023 Thigh = +70C for MC34023 = -40C for MC33023 = +105C for MC33023
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ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kW, CT = 1.0 nF, for typical values TA = + 25C, for min/max values TA
is the operating ambient temperature range that applies [Note 3], unless otherwise noted.) Characteristic CURRENT SENSE SECTION Input Bias Current (Pin 9(12) = 0 V to 4.0 V) Current Limit Comparator Input Offset Voltage (Pin 11(14) = 1.1 V) Current Limit Reference Input Common Mode Range (Pin 11(14)) TJ = + 25C Shutdown Comparator Threshold Propagation Delay (Current Limit/Shutdown to Output, TJ = + 25C) OUTPUT SECTION Output Voltage Low State (ISink = 20 mA) (ISink = 200 mA) High State (ISource = 20 mA) (ISource = 200 mA) Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 0.5 mA) Output Leakage Current (VC = 20 V) Output Voltage Rise Time (CL = 1.0 nF, TJ = + 25C) Output Voltage Fall Time (CL = 1.0 nF, TJ = + 25C) UNDERVOLTAGE LOCKOUT SECTION Startup Threshold (VCC Increasing) UVLO Hysteresis Voltage (VCC Decreasing After Turn-On) TOTAL DEVICE Power Supply Current Startup (VCC = 8.0 V) Operating ICC - - 0.5 20 1.2 30 mA Vth(on) VH 8.8 0.4 9.2 0.8 9.6 1.2 V V V VOL VOH VOL(UVLO) IL tr tf - - 13 12 - - - - 0.25 1.2 13.5 13 0.25 100 30 30 0.4 2.2 - - 1.0 500 60 60 V mA ns ns IIB VIO VCMR Vth tPLH(in/out) - - 1.0 1.25 - - - - 1.40 50 15 45 3.0 1.55 80 mA mV V V ns Symbol Min Typ Max Unit
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0C for MC34023 Thigh = +70C for MC34023 = -40C for MC33023 = +105C for MC33023
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MC34023, MC33023
100 k 1 R T , TIMING RESISTOR ( ) 3 2 5 4 7 6 9 8 f osc, OSCILLATOR FREQUENCY (kHz) VCC = 15 V TA = + 25C 1200 1000 800 VCC = 15 V 600 400 kHz 400 200 50 kHz 0 - 55 - 25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) RT = 3.6 k CT = 1.0 nF RT = 36 k CT = 1.0 nF 100 125 1.0 MHz RT = 1.2 k CT = 1.0 nF
CT = 10 k 1. 100 nF 2. 47 nF 3. 22 nF 4. 10 nF 5. 4.7 nF 6. 2.2 nF 1.0 k 7. 1.0 nF 8. 470 pF 9. 220 pF 470 104 105 106 100 1000 fosc, OSCILLATOR FREQUENCY (Hz)
107
Figure 2. Timing Resistor versus Oscillator Frequency
Figure 3. Oscillator Frequency versus Temperature
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
120 100 80 60 Phase 40 20 0 - 20 10 100 1.0 k 10 k 100 k f, FREQUENCY (Hz) 1.0 M
0 , EXCESS PHASE (C) VTH, ZERO DUTY CYCLE (V)
1.30 1.28 VCC = 15 V Pin 7(9) = 0 V 1.26 1.24 1.22 1.20 - 55
45 Gain
90
135 10 M
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 4. Error Amp Open Loop Gain and Phase versus Frequency
Figure 5. PWM Comparator Zero Duty Cycle Threshold Voltage versus Temperature
2.55 V
3.0 V
2.5 V
2.5 V
2.45 V 0.1 ms/DIV
2.0 V 0.1 ms/DIV
Figure 6. Error Amp Small Signal Transient Response
Figure 7. Error Amp Large Signal Transient Response
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Vref , REFERENCE VOLTAGE CHANGE (mV) 0 - 5.0 VCC = 15 V - 10 TA = +125C - 15 - 20 - 25 - 30 0 10 20 30 40 ISource, SOURCE CURRENT (mA) 50 TA = + 25C I SC, REFERENCE SHORT CIRCUIT CURRENT (mA 66 65.6 65.2 64.8 64.4 64 - 55 VCC = 15 V
TA = - 55C
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 8. Reference Voltage Change versus Source Current
Figure 9. Reference Short Circuit Current versus Temperature
2.0 mV/DIV
Vref LINE REGULATION 10 V to 24 V (2.0 ms/DIV)
2.0 mV/DIV
Vref LOAD REGULATION 1.0 mA to 10 mA (2.0 ms/DIV)
Figure 10. Reference Line Regulation
Figure 11. Reference Load Regulation
VIO, CURRENT LIMIT INPUT OFFSET VOLTAGE (mV)
100 60 20 - 20 - 60 - 100 - 55 VCC = 15 V Pin 11(14) = 1.1 V Vth, THRESHOLD VOLTAGE (V)
1.50 1.46 1.42 1.38 1.34 1.30 - 55 VCC = 15 V
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 12. Current Limit Comparator Input Offset Voltage versus Temperature
Figure 13. Shutdown Comparator Threshold Voltage versus Temperature
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I chg, SOFT-START CHARGE CURRENT ( A) Vsat , OUTPUT SATURATION VOLTAGE (V) 10 VCC = 15 V 9.5 9.0 8.5 8.0 7.5 7.0 - 55 0 VCC VCC = 15 V 80 ms Pulsed Load 120 Hz Rate TA = 25C Source Saturation (Load to Ground)
- 1.0
- 2.0
2.0 1.0 Ground 0 0 0.2 Sink Saturation (Load to VCC) 1.0
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
0.4 0.6 0.8 IO, OUTPUT LOAD CURRENT (A)
Figure 14. Soft-Start Charge Current versus Temperature
Figure 15. Output Saturation Voltage versus Load Current
OUTPUT RISE & FALL TIME 1.0 nF LOAD 50 ns/DIV
OUTPUT RISE & FALL TIME 10 nF LOAD 50 ns/DIV
Figure 16. Drive Output Rise and Fall Time
Figure 17. Drive Output Rise and Fall Time
30 I CC , SUPPLY CURRENT (mA) 25 20 VCC Increasing 15 VCC Decreasing 10 5.0 0 0 4.0 8.0 12 VCC, SUPPLY VOLTAGE (V) 16 20 RT = 3.65 kW CT = 1.0 nF
Figure 18. Supply Voltage versus Supply Current
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MC34023, MC33023
VCC Vin
16 Vref Clock 4 5 RT CT Oscillator 6 PWM Comparator 4.2 V
Reference Regulator
15 VCC UVLO 9.2 V VCC 13 VC 14 R S Q PWM Latch Output 12 Power Ground
Vref UVLO
Ramp Error Amp Output
7 3 2
1.25 V
Noninverting Input Inverting Input Soft-Start CSS
Error Amp
+ 9.0 mA
Current Limit
11 Current Limit Reference 9 Current Limit/Shutdown
1 8 R Q S 10 Ground 0.5 V Soft-Start Latch 1.4 V Shutdown
Figure 19. Representative Block Diagram
CT
Clock
Soft-Start Error Amp Output Ramp
PWM Comparator
Output
Figure 20. Current Limit Operating Waveforms
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MC34023, MC33023
OPERATING DESCRIPTION The MC33023 and MC34023 series are high speed, fixed frequency, single-ended pulse width modulator controllers optimized for high frequency operation. They are specifically designed for Off-Line and DC-to-DC converter applications offering the designer a cost effective solution with minimal external components. A representative block diagram is shown in Figure 19.
Oscillator
output of the error amplifier to less than its normal output voltage, thus limiting the duty cycle. The time it takes for a capacitor to reach full charge is given by:
t [ (4.5 * 10 5) C Soft-Start
The oscillator frequency is programmed by the values selected for the timing components RT and CT. The RT pin is set to a temperature compensated 3.0 V. By selecting the value of RT, the charge current is set through a current mirror for the timing capacitor CT. This charge current runs continuously through CT. The discharge current is ratioed to be 10 times the charge current, which yields the maximum duty cycle of 90%. CT is charged to 2.8 V and discharged to 1.0 V. During the discharge of CT, the oscillator generates an internal blanking pulse that resets the PWM Latch and, inhibits the outputs. The threshold voltage on the oscillator comparator is trimmed to guarantee an oscillator accuracy of 5.0% at 25C. Additional dead time can be added by externally increasing the charge current to CT as shown in Figure 24. This changes the charge to discharge ratio of CT which is set internally to Icharge/10 Icharge. The new charge to discharge ratio will be:
% Deadtime + I additional ) I charge 10 (I charge)
A Soft-Start latch is incorporated to prevent erratic operation of this circuitry. Two conditions can cause the Soft-Start circuit to latch so that the Soft-Start capacitor stays discharged. The first condition is activation of an undervoltage lockout of either VCC or Vref. The second condition is when current sense input exceeds 1.4 V. Since this latch is "set dominant", it cannot be reset until either of these signals is removed and, the voltage at CSoft-Start is less than 0.5 V.
PWM Comparator and Latch
A PWM circuit typically compares an error voltage with a ramp signal. The outcome of this comparison determines the state of the output. In voltage mode operation the ramp signal is the voltage ramp of the timing capacitor. In current mode operation the ramp signal is the voltage ramp induced in a current sensing element. The ramp input of the PWM comparator is pinned out so that the user can decide which mode of operation best suits the application requirements. The ramp input has a 1.25 V offset such that whenever the voltage at this pin exceeds the error amplifier output voltage minus 1.25 V, the PWM comparator will cause the PWM latch to set, disabling the outputs. Once the PWM latch is set, only a blanking pulse by the oscillator can reset it, thus initiating the next cycle.
Current Limiting and Shutdown
A bidirectional clock pin is provided for synchronization or for master/slave operation. As a master, the clock pin provides a positive output pulse during the discharge of CT. As a slave, the clock pin is an input that resets the PWM latch and blanks the drive output, but does not discharge CT. Therefore, the oscillator is not synchronized by driving the clock pin alone. Figures 28, 29 and 30 provide suggested synchronization.
Error Amplifier
A fully compensated Error Amplifier is provided. It features a typical DC voltage gain of 95 dB and a gain bandwidth product of 8.3 MHz with 75 degrees of phase margin (Figure 4). Typical application circuits will have the noninverting input tied to the reference. The inverting input will typically be connected to a feedback voltage generated from the output of the switching power supply. Both inputs have a common mode voltage (VCM) input range of 1.5 V to 5.5 V. The Error Amplifier Output is provided for external loop compensation.
Soft-Start Latch
A pin is provided to perform current limiting and shutdown operations. Two comparators are connected to the input of this pin. The reference voltage for the current limit comparator is not set internally. A pin is provided so the user can set the voltage. When the voltage at the current limit input pin exceeds the externally set voltage, the PWM latch is set, disabling the output. In this way cycle-by-cycle current limiting is accomplished. If a current limit resistor is used in series with the power devices, the value of the resistor is found by:
R Sense + I Limit Reference Voltage I pk (switch)
Soft-Start is accomplished in conjunction with an external capacitor. The Soft-Start capacitor is charged by an internal 9.0 mA current source. This capacitor clamps the
If the voltage at this pin exceeds 1.4 V, the second comparator is activated. This comparator sets a latch which, in turn, causes the soft start capacitor to be discharged. In this way a "hiccup" mode of recovery is possible in the case of output short circuits. If a current limit resistor is used in series with the output devices, the peak current at which the controller will enter a "hiccup" mode is given by:
I shutdown + 1.4 V R Sense
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MC34023, MC33023
In certain applications, it may be desirable to disable the current limit comparator. This can be accomplished by biasing pin 11 to a level greater than 1.4 V but less than 3.0 V. Under these conditions, the shutdown comparator and soft-start latch are activated during an overcurrent event causing the converter to enter an hiccup mode.
Undervoltage Lockout
specific part in question. The PC board lead lengths must be less than 0.5 inches for effective bypassing for snubbing.
Instabilities
There are two undervoltage lockout circuits within the IC. The first senses VCC and the second Vref. During power-up, VCC must exceed 9.2 V and Vref must exceed 4.2 V before the outputs can be enabled and the Soft-Start latch released. If VCC falls below 8.4 V or Vref falls below 3.6 V, the outputs are disabled and the Soft-Start latch is activated. When the UVLO is active, the part is in a low current standby mode allowing the IC to have an off-line bootstrap startup circuit. Typical startup current is 500 mA.
Output
In current mode control, an instability can be encountered at any given duty cycle. The instability is caused by the current feedback loop. It has been shown that the instability is caused by a double pole at half the switching frequency. If an external ramp (Se) is added to the on-time ramp (Sn) of the current-sense waveform, stability can be achieved. One must be careful not to add too much ramp compensation. If too much is added the system will start to perform like a voltage mode regulator. All benefits of current mode control will be lost. Figure 26 is an example of one way in which external ramp compensation can be implemented.
Ramp Compensation
The MC34023 has a high current totem pole output specifically designed for direct drive of power MOSFETs. It is capable of up to 2.0 A peak drive current with a typical rise and fall time of 30 ns driving a 1.0 nF load. Separate pins for VC and Power Ground are provided. With proper implementation, a significant reduction of switching transient noise imposed on the control circuitry is possible. The separate VC supply input also allows the designer added flexibility in tailoring the drive voltage independent of VCC.
Reference
Ramp Input Ramp Compensation Se Current Signal Sn 1.25 V
Figure 21. Ramp Compensation
A 5.1 V bandgap reference is pinned out and is trimmed to an initial accuracy of 1.0% at 25C. This reference has short circuit protection and can source in excess of 10 mA for powering additional control system circuitry.
Design Considerations
A simple equation can be used to calculate the amount of external ramp slope necessary to add that will achieve stability in the current loop. For the following equations, the calculated values for the application circuit in Figure 35 are also shown.
Se + VO L NS NP (R S)Ai
Do not attempt to construct the converter on wire-wrap or plug-in prototype boards. With high frequency, high power, switching power supplies it is imperative to have separate current loops for the signal paths and for the power paths. The printed circuit layout should contain a ground plane with low current signal and high current switch and output grounds returning on separate paths back to the input filter capacitor. Shown in Figure 36 is a printed circuit layout of the application circuit. Note how the power and ground traces are run. All bypass capacitors and snubbers should be connected as close as possible to the
where:
VO = NP, NS = = Ai = = L= RS =
DC output voltage number of power transformer primary or secondary turns gain of the current sense network (see Figures 24 and 25) output inductor current sense resistance
5 2 (0.3)(0.55) For the application circuit: S e + 1.8 8 = 0.115 V/ms
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PIN FUNCTION DESCRIPTION
Pin DIP/SOIC 1 2 Function Error Amp Inverting Input Error Amp Noninverting Input Error Amp Output Clock RT CT Ramp Input Soft-Start Current Limit/ Shutdown Ground Current Limit Reference Input Power Ground VC Description This pin is usually used for feedback from the output of the power supply. This pin is used to provide a reference in which an error signal can be produced on the output of the error amp. Usually this is connected to Vref, however an external reference can also be used. This pin is provided for compensating the error amp for poles and zeros encountered in the power supply system, mostly the output LC filter. This is a bidirectional pin used for synchronization. The value of RT sets the charge current through timing Capacitor, CT. In conjunction with RT, the timing Capacitor sets the switching frequency. For voltage mode operation this pin is connected to CT. For current mode operation this pin is connected through a filter to the current sensing element. A capacitor at this pin sets the Soft-Start time. This pin has two functions. First, it provides cycle-by-cycle current limiting. Second, if the current is excessive, this pin will reinitiate a Soft-Start cycle. This pin is the ground for the control circuitry. This pin voltage sets the threshold for cycle-by-cycle current limiting. This is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. This is a separate power source connection for the outputs that is connected back to the power source input. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. This is a high current totem pole output. This pin is the positive supply of the control IC. This is a 5.1 V reference. It is usually connected to the noninverting input of the error amplifier.
3 4 5 6 7 8 9 10 11 12 13
14 15 16
Output VCC Vref
4 5 Oscillator CT 6 CT From Current Sense Element
4 5 Oscillator 6
7 3 1 Output Voltage Feedback Input Vref 2
1.25 V
7 3 1
1.25 V
Output Voltage Feedback Input
Vref
2
In voltage mode operation, the control range on the output of the Error Amplifier from 0% to 90% duty cycle is from 2.25 V to 4.05 V.
In current mode control, an RC filter should be placed at the ramp input to filter the leading edge spike caused by turn-on of a power MOSFET.
Figure 22. Voltage Mode Operation
Figure 23. Current Mode Operation
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MC34023, MC33023
9
9 ISense
Rw
ISense
The addition of an RC filter will eliminate instability caused by the leading edge spike on the current waveform. This sense signal can also be used at the ramp input pin for current mode control. For ramp compensation it is necessary to know the gain of the current feedback loop. If a transformer is used, the gain can be calculated by: R Sense turns ratio
The addition of an RC filter will eliminate instability caused by the leading edge spike on the current waveform. This sense signal can also be used at the ramp input pin for current mode control. For ramp compensation it is necessary to know the gain of the current feedback loop. The gain can be calculated by:
Ai
+
Ai
+
Rw turns ratio
Figure 24. Resistive Current Sensing
Figure 25. Primary Side Current Sensing
4 5 6 CT R1 R2 C1 7 3 1.25 V Oscillator
Current Sense Information
This method of slope compensation is easy to implement, however, it is noise sensitive. Capacitor C1 provides AC coupling. The oscillator signal is added to the current signal by a voltage divider consisting of resistors R1 and R2.
Figure 26A. Slope Compensation (Noise Sensitive)
Current Sense Transformer Rw Output RM CM Rf Cf 3 Ramp Input 7 1.25 V
Figure 26.
Output Ramp Input RM CM Current Sense Resistor Rf Cf 7 3 1.25 V
When only one output is used, this method of slope compensation can be used and it is relatively noise immune. Resistor RM and capacitor CM provide the added slope necessary. By choosing RM and CM with a larger time constant than the switching frequency, you can assume that its charge is linear. First choose CM, then RM can be adjusted to achieve the required slope. The diode provides a reset pulse at the ramp input at the end of every cycle. The charge current IM can be calculated by IM = CMSe. Then RM can be calculated by RM = VCC/IM.
Figure 26B. Slope Compensation (Noise Immune)
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MC34023, MC33023
5.0 V 0V 4 5 6 RT Vref RDT 4 5 6 RT CT Oscillator CT Oscillator
Additional dead time can be added by the addition of a dead time resistor from Vref to CT. See text on Oscillator section for more information.
The sync pulse fed into the clock pin must be at least 3.9 V. RT and CT need to be set 10% slower than the sync frequency. This circuit is also used in Voltage Mode operation for master/slave operation. The clock signal would be coming from the master which is set at the desired operating frequency, while the slave is set 10% slower.
Figure 27. Dead Time Addition
Figure 28. External Clock Synchronization
4 5 Master Oscillator 6 CT RT Vref
4 5 6 Slave Oscillator
Figure 29. Current Mode Master/Slave Operation Over Short Distances
Reference
16 1.0 k
20 MMBT3906 4 4.7 k NC MMBD0914 430 MMBT3904 CT RT CT 1.15 RT 5 6 Slave Oscillator
4 5 Master Oscillator 6
2200
Figure 30. Synchronization Over Long Distances
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MC34023, MC33023
1 2 Vref R1 R2 8 CSS + 0 - Base Charge Removal 15 VC Vin
+ IB
In voltage mode operation, the maximum duty cycle can be clamped. By the addition of a PNP transistor to buffer the clamp voltage, the Soft-Start current is not affected by R1. The new equation for Soft-Start is t[ V clamp ) 0.6 9.0 A
14 12 To Current Sense Input RS
(CSS)
The totem pole output can furnish negative base current for enhanced transistor turn-off, with the addition of the capacitor in series with the base.
In current mode operation, this circuit will limit the maximum voltage allowed at the ramp input to end a cycle.
Figure 31. Buffered Maximum Clamp Level
Figure 32. Bipolar Transistor Drive
VC
Vin VC
15 14 15 14 12 To Current Sense Input RS 12
A series gate resistor may be needed to dampen high frequency parasitic oscillation caused by the MOSFET's input capacitance and any series wiring inductance in the gate-source circuit. The series resistor will also decrease the MOSFET switching speed. A Schottky diode can reduce the driver's power dissipation due to excessive ringing, by preventing the output pin from being driven below ground. The Schottky diode also prevents substrate injection when the output pin is driven below ground.
The totem pole output can easily drive pulse transformers. A Schottky diode is recommended when driving inductive loads at high frequencies. The diode can reduce the driver's power dissipation due to excessive ringing, by preventing the output pin from being driven below ground.
Figure 33. MOSFET Parasitic Oscillations
Figure 34. Isolated MOSFET Drive
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V in = 40 V to 56 V 1N5819 Vref 16 4 5 Oscillator 10 IRF640 50 MUR410 1600 pF 7 3 1 2 + 8 0.5 V 47 1.4 V Soft-Start Latch 220 pF R Q S Error Amp 9.0 A Shutdown 9 100 1.0 k PWM Latch Current Limit 11 3.9 k 100 S 1N5819 1.25 V Q 12 0.3 2 PWM Comparator R 14 4.7 6 Vref UVLO 9.2 V MBR2535 CTL 4.2 V 13 VCC UVLO 47 100 Reference Regulator 10 15 47 k T1 1.8 4.7 1500 pF 22 VO = 5.0 V
1.0 1.2 k
10 F L1 22 1500 pF 1
1000 pF
0.01
22 k
2.0 k Vref
0.015 F
47 k 0.1 Soft-Start
MC34023, MC33023
Figure 35. Application Circuit
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10 Test Line Regulation Load Regulation Output Ripple Efficiency
T1 - Primary: 8 turns #48 AWG (1300 strands litz wire) Secondary: 2 turns 0.003'' (2 layers) copper foil Bootstrap: 1 turn added to secondary #36 AWG Core: Philips 3F3, part #4312 020 4124 Bobbin: Philips part #4322 021 3525 Coilcraft P3269-A L1 - 2 turns #48 AWG (1300 strands litz wire) Core: Philips 3F3, part #EP10-3F3 Bobbin: Philips part #EP10PCB1-8 L = 1.8 H Coilcraft P3270-A 1 - 10(1.0 F) ceramic capacitors in parallel 2 - 5(1.5 ) resistors in parallel
15
Condition V in = 40 V to 56 V, IO = 7.5A V in = 48 V, IO = 4.0 A to 7.5 A V in = 48 V, IO = 7.5 A V in = 48 V, IO = 7.5 A
Result 14 mV = 0.275% 54 mV = 1.0% 10 mVp-p 69.8%
Heatsinks - Power FET: AAVID Heatsink #533902B02552 with clip Output Rectifiers: AAVID Heatsink #533402B02552 with clip
Insulators - All power devices are insulated with Berquist Sil-Pad 150
MC34023, MC33023
1N5819
1N5819
MBR 2535CTI
1500 pF
100 pF
4.0
1N5819 +10
100 pF
MC34023
1000 pF 0.01
0.01
0.01
100
2200 pF
MBR 2535CTI
1500 pF
6.5 (Top View) Figure 36. PC Board With Components
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16
MC34023, MC33023
(Top View)
4.0
6.5 (Bottom View) Figure 37. PC Board Without Components http://onsemi.com
17
MC34023, MC33023
PACKAGE DIMENSIONS
PDIP-16 P SUFFIX CASE 648-08 ISSUE T
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16W DW SUFFIX CASE 751G-03 ISSUE C
D
16 M 9
A
q
h X 45_
0.25
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_
H
M
B
8X
1
8
16X
B TA
S
0.25
M
B
S
A
E B
A1
14X
e
SEATING PLANE
T
C
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MC34023/D

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